CYK001M16ZCCA

Features:

• Wide voltage range: 2.70V3.30V
• Access Time: 55 ns, 70 ns
• Ultra-low active power
- Typical active current: 3 mA @ f = 1 MHz
- Typical active current: 13 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a 48-ball BGA Package


Pinout




Specifications

Storage Temperature ..........................................................................65°C to + 150°C
Ambient Temperature with Power Applied............................................55°C to + 125°C
Supply Voltage to Ground Potential .............................................................. 0.4V to 4.6V
in High Z State^{[6, 7, 8]} ...................................................................................0.4V to 3.7V
DC Input Voltage^{[6, 7, 8]}................................................................................0.4V to 3.7V
Output Current into Outputs (LOW)........................................................................... 20 mA
Static Discharge Voltage......................................................................................... > 2001V
(per MIL-STD-883, Method 3015) Latch-Up Current...............................................> 200 mA


Description

The CYK001M16ZCCAU is a high-performance CMOS Pseudo static RAM organized as 1M words by 16 bits that supports an asynchronous memory interface. The  CYK001M16ZCCAU  features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device can be put into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).
Writing to the CYK001M16ZCCAU is accomplished by asserting Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).
Reading from the CYK001M16ZCCAU is accomplished by asserting Chip Enable (CE) and Output Enable (OE) inputs LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) LOW, then data from the memory location specified by the address pins of the  CYK001M16ZCCAU will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 I/O15. Refer to the truth table for a complete description of read and write modes.
The  CYK001M16ZCCAU  incorporates a Low Power mode wherein data integrity is not guaranteed, but Power Consumption reduces to less than 100 µW. This mode (Deep Sleep Mode) is enabled by driving ZZ LOW.See the Truth Table for a complete description of Read, Write, and Deep Sleep mode.