Cellular Memory (M18) Selling Leads, Price trend, Cellular Memory (M18) DataSheet download, circuit diagram from SeekIC.com

Features: `􀂄 High-Performance Read, Program and Erase- 96 ns initial read access- 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output- 133 MHz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output- 8-, 16-, and continuous-word synchronous-bu...

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SeekIC No. : 004312846 Detail

Cellular Memory (M18): Features: `􀂄 High-Performance Read, Program and Erase- 96 ns initial read access- 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output- 133 MHz with zero wait-sta...

Cellular Memory (M18) Data Sheet

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Part Number:: Cellular Memory (M18)
Supply Ability:: 5000

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1~5000

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Negotiable

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15 Days

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Product Details

Description

Features:

`􀂄 High-Performance Read, Program and Erase
- 96 ns initial read access
- 108 MHz with zero wait-state synchronous burst reads: 7 ns clock-to-data output
- 133 MHz with zero wait-state synchronous burst reads: 5.5 ns clock-to-data output
- 8-, 16-, and continuous-word synchronous-burst Reads
- Programmable WAIT configuration
- Customer-configurable output driver impedance
- Buffered Programming:
2.0 s/Word (typ), 512-Mbit 65 nm;
Block Erase: 0.9 s per block (typ)
- 20 s (typ) program/erase suspend
`􀂄 Architecture
- 16-bit wide data bus
- Multi-Level Cell Technology
- Symmetrically-Blocked Array Architecture
- 256-Kbyte Erase Blocks
- 1-Gbit device: Eight 128-Mbit partitions
- 512-Mbit device: Eight 64-Mbit partitions
- 256-Mbit device: Eight 32-Mbit partitions.
- 128-Mbit device: Eight 16-Mbit partitions.
- Read-While-Program and Read-While-Erase
- Status Register for partition/device status
- Blank Check feature
`􀂄 Quality and Reliability
- Expanded temperature: 30 °C to +85 °C
- Minimum 100,000 erase cycles per block
- ETOX™ X Process Technology (65 nm)
- ETOX™ IX Process Technology (90 nm)
`􀂄 Power
- Core voltage: 1.7 V - 2.0 V
- I/O voltage: 1.7 V - 2.0 V
- Standby current: 60 A (typ) for 512-Mbit, 65 nm
- Deep Power-Down mode: 2 A (typ)
- Automatic Power Savings mode
- 16-word synchronous-burst read current:
23 mA (typ) @ 108 MHz; 24 mA (typ) @ 133 MHz
`􀂄 Software
- Numonyx™ Flash Data Integrator (Numonyx™ FDI) optimized
- Basic Command Set and Extended Command Set compatible
- Common Flash Interface
`􀂄 Security
- OTP Registers:
64 unique pre-programmed bits
2112 user-programmable bits
- Absolute write protection with VPP = GND
- Power-transition erase/program lockout
- Individual zero-latency block locking
- Individual block lock-down
`􀂄 Density and Packaging
- Density: 128-, 256-, and 512-Mbit, and 1- Gbit
- Address-data multiplexed and nonmultiplexed interfaces
- x16D (105-ball) Flash SCSP
- x16C (107-ball) Flash SCSP
- 0.8 mm pitch lead-free solder-ball

Specifications

Parameter	Min	Max	Unit	Conditions	Notes
Temperature under Bias Expanded	-30	+85	°C	-	1
Storage Temperature	65	+125	°C	-	1
F-VCC Voltage	2.0	V_CCQ + 2.0	V	-	2,3
VCCQ and P-VCC Voltage	2.0	V_CCQ + 2.0	V	-	2,4
Voltage on any input/output signal (except VCC, VCCQ,and VPP)	2.0	V_CCQ + 2.0	V	-	2,4
F-VPP Voltage	2.0	+11.5	V	-	2,3
I_SH Output Short Circuit Current	-	100	mA	-	5
V_PPH Time	-	80	Hours	-	6
Block Program/Erase Cycles: Main Blocks	100,000	-	Cycles	F-VPP = V_CCor F-VPP = V_PPH	6

Notes:
1. Temperature is Ambient, not Case.
2. Voltage is referenced to VSS.
3. During signal transitions, minimum DC voltage may undershoot to 2.0 V for periods < 20 ns; maximum DC voltage
may overshoot to V_CC (max) + 2.0 V for periods < 20 ns.
4. During signal transitions, minimum DC voltage may undershoot to 1.0 V for periods < 20 ns; maximum DC voltage
may overshoot to V_CCQ (max) + 1.0 V for periods < 20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
6. Operation beyond this limit may degrade performance.

Description

The Numonyx™ StrataFlash^® Cellular Memory (M18) device provides high read and write performance at low voltage on a 16-bit data bus.

Cellular Memory (M18) has a multi-partition architecture with read-while-program and read-while-erase capability.

Cellular Memory (M18) supports synchronous burst reads up to 108 MHz using ADV# and CLK address-latching on some litho/density combinations and up to 133 MHz using CLK address-latching only on some litho/density combinations. It is listed below in the following table.

Cellular Memory (M18)

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