D555

The ALD555 timer is a high performance monolithic timing circuit built withadvanced silicon gate CMOS technology. D555 offers the benefits of highinput impedance, thereby allowing smaller timing capacitors and longertiming cycle; high speed, with typical cycle time of 500ns; low powerdissipation for battery operated environment; reduced supply currentspikes, allowing smaller and lower cost decoupling capacitors. It iscapable of producing accurate time delays and oscillations in bothmonostable and astable operation. D555 operates in the one-shot (monostable)mode or 50% duty cycle free running oscillation mode with a singleresistor and one capacitor. The inputs and outputs are fully compatiblewith CMOS, NMOS or TTL logic.

There are three matched internal resistors (approximately 200K  each)that set the threshold and trigger levels at two-thirds andone-thirdrespectively of V+. These levels can be adjusted by using the controlterminal (pin 5). When the trigger input isbelow the trigger level, theoutput is in the high state and sourcing 2mA. When threshold input isabove the threshold level at the sametime the trigger input is above thetrigger level, the internal flip-flop is reset, the output goes to the low stateand sinksup to 10mA. The reset input overrides all other inputs and whenit is active (reset voltage less than 1V), the output is in the low state.