DG538A

The DG534A is a digitally selectable 4-channel or dual 2-channel multiplexer. The DG538A is an 8-channel or dual 4-channel multiplexer. On-chip TTL-compatible address decoding logic and latches with data readback are included to simplify the interface to a microprocessor data bus. The low on-resistance and low capacitance of the these devices make them ideal for wideband data multiplexing and video and audio signal routing in channel selectors and crosspoint arrays. An optional negative supply pin allows the handling of bipolar signals without dc biasing.

The DG534A/DG538A are built on a D/CMOS process that combines n-channel DMOS switching FETs with low-power
CMOS control logic, drivers and latches. The low-capacitance DMOS FETs are connected in a "T" configuration to achieve extremely high levels of off isolation. Crosstalk is reduced to 97 dB at 5 MHz by including a ground line between adjacent signal paths. An epitaxial layer prevents latch-up.