DM54L72

  This DM54L72 device contains a positive pulse triggered master-slave J-K flip-flop with complementary outputs Multiple J and K inputs are ANDed together to produce the internal J and K function for the flip-flop. The J and K data is processed by the flip-flop after a complete clock pulse While the clock is low the slave is isolated from the master. On the positive transition of the clock the data from the AND gates is trans- ferred to the master While the clock is high the AND gate inputs are disabled On the negative transition of the clock the data from the master is transferred to the slave The logic state of the J and K inputs must not be allowed to change while the clock is in the high state Data is trans-ferred to the outputsof DM54L72  on the falling edge of the clock pulse A low logic level on the preset or clear inputs sets or resets the outputs regardless of the logic levels of the other inputs