DM54L73

  This DM54L73 device contains two independent positive pulse trig-gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse While the clock is low the slave is isolated from the master. On the positive transition of the clock the data from he J and K inputs is transferred to the master. While the clock is high the data from the J and K inputs are disabled On the negative transition of the clock the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is high Data is transferred to the outputs of DM54L73 on the falling edge of the clock pulse A low logic level on the clear input will reset the outputs regardless of the logic states of the other inputs