DM54LS368A

Features: Alternate Military/Aerospace device (54LS368) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.SpecificationsSupply Voltage 7VInput Voltage 7VOperating Free Air Temperature Range DM54LS and 54LS-55 to +125 DM74LS0 to +70Storage Temperature Range ...

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SeekIC No. : 004326993 Detail

DM54LS368A: Features: Alternate Military/Aerospace device (54LS368) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.SpecificationsSupply Voltage 7VInput Voltage 7VOper...

floor Price/Ceiling Price

Part Number:
DM54LS368A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/5

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Product Details

Description



Features:

Alternate Military/Aerospace device (54LS368) is available. Contact a National Semiconductor Sales Office/Distributor for specifications.


Specifications

Supply Voltage                                                                            7V
Input Voltage                                                                              7V
Operating Free Air Temperature Range
    DM54LS and 54LS                                               -55 to +125
    DM74LS                                                                    0 to +70
Storage Temperature Range                                   -65 to +150




Description

This DM54LS368A device contains six independent gates each of which performs an inverting buffer function. The outputs have the TRI-STATE feature. When enabled, the outputs of DM54LS368A exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned off presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs of DM54LS368A  will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.




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