DM74LS166

These parallel-in or serial-in, serial-out shift registers fea-ture gated clock inputs and an overriding clear input. All inputs are buffered to lower the drive requirements to onenormalized load, and input clamping diodes minimize switching transients to simplify system design. The loadmode is established by the shift/load input. When HIGH,this input enables the serial data input and couples theeight flip-flops for serial shifting with each clock pulse.When LOW, the parallel (broadside) data inputs areenabled and synchronous loading occurs on the next clockpulse. Duringparallel loading, serial data flow is inhibited.

Clocking is accomplished on the LOW-to-HIGH level edgeof the clock pulse through a two-input NOR gate, permitting one input to be used as a clock-enable or clock-inhibit func-tion. Holding either of the clock inputs HIGH inhibits clock-ing; holding either LOW enables the other clock input. Thisallows the system clock to be free running, and the register
can be stopped on command with the other clock input.The clock-inhibit input should be changed to the high levelonly while the clock input is HIGH. A buffered, direct clearinput overrides all other inputs, including the clock, andsets all flip-flops to zero.