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Part Number: DM9801
Description: The DM9801 is a physical-layer, single-chip, low-power transceiver for 1M Home Phoneline Networ...
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DM9801
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General Description
DM9801 General Description
The DM9801 is a physical-layer, single-chip, low-power transceiver for 1M Home Phoneline Network applications. On the media side, it provides an interface to a Home Phoneline wiring system. The reconciliation layer interfaces to the DM9801 either through an IEEE802.3u subset Media Independent Interface (MII) or a pseudo-standard General Purpose Serial Interface (GPSI). A management interface is provided by MDIO/MDC when operating in MII mode, or a Serial Peripheral Interface bus when operating in GPSI mode.
The DM9801 uses a low-power and high-performance CMOS process. It contains the entire physical layer functions of 1M as defined by Home Phoneline Network Alliance, Rev. 1.1, including the Physical Coding Sublayer, (RLL25) Encoder/Decoder (ENC/DEC), 4-wire HN Driver circuit and receiver analog front end (AFE).
DM9801 Maximum Ratings
| Symbol | Parameter | Min. | Max. | Unit | Conditions |
| DVCC,AVCC | Supply Voltage | -0.3 | 3.6 | V | |
| VIN | DC Input Voltage (VIN) | -0.5 | 5.5 | V | |
| VOUT | DC Output Voltage(VOUT) | -0.3 | 3.6 | V | |
| T A | Ambient Temperature Range | 0 | 70 | ||
| Tc | Case Temperature Range | 0 | 85 | @ TA= 70 | |
| Tstg | Storage Temperature Rang (Tstg) | -40 | +125 | ||
| PD | Power Dissipation (PD) | --- | 0.43 | W | |
| LT | Lead Temp. (TL, Soldering, 10 sec.) | --- | 235 | ||
| ESD | ESD rating (Rzap=1.5K,Czap=100pF) | --- | 2000 | V |
DM9801 Features
*1M Home Phoneline Network physical-layer, single-chip transceiver
*Supports the MII including the MDIO/MDC serial management interface
*Supports the GPSI including a SPI serial
*management interface
*Supports Link Integrity function
*Smart equalizer circuit for 1M receiver
*Supports Patent Pending 4-wire operation
*Supports hardware or software speed select
*Supports Interrupt on change, eliminates management polling
*Flexible built-in LED support for TX Activity, RX Activity and Collision Indication or Activity, Link state and Collision
*Digital PLL circuit using advanced digital algorithm to reduce jitter
*Low-power, high-performance CMOS process
*Available in a small outline 100-pin LQFP
*3.3V DC power with 5V DC tolerant I/O
*Supports the MII including the MDIO/MDC serial management interface
*Supports the GPSI including a SPI serial
*management interface
*Supports Link Integrity function
*Smart equalizer circuit for 1M receiver
*Supports Patent Pending 4-wire operation
*Supports hardware or software speed select
*Supports Interrupt on change, eliminates management polling
*Flexible built-in LED support for TX Activity, RX Activity and Collision Indication or Activity, Link state and Collision
*Digital PLL circuit using advanced digital algorithm to reduce jitter
*Low-power, high-performance CMOS process
*Available in a small outline 100-pin LQFP
*3.3V DC power with 5V DC tolerant I/O
DM9801 Connection Diagram
DM9801
PDF/DataSheet Download
- Datasheet: DM9801
- File Size: 604075 KB
- Manufacturer: ETC [ETC]
- Click here to Download
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