DP83932C-25

Features: ·32-bit non-multiplexed address and data bus·High-speed, interruptible DMA·Linked-list buffer management maximizes flexibility·Two independent 32-byte transmit and receive FIFOs·Bus compatibility for all standard microprocessors·Supports big and little endian formats·Integrated IEEE 802....

product image

DP83932C-25 Picture
SeekIC No. : 004327982 Detail

DP83932C-25: Features: ·32-bit non-multiplexed address and data bus·High-speed, interruptible DMA·Linked-list buffer management maximizes flexibility·Two independent 32-byte transmit and receive FIFOs·Bus compat...

floor Price/Ceiling Price

Part Number:
DP83932C-25
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/5/3

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

·32-bit non-multiplexed address and data bus
·High-speed, interruptible DMA
·Linked-list buffer management maximizes flexibility
·Two independent 32-byte transmit and receive FIFOs
·Bus compatibility for all standard microprocessors
·Supports big and little endian formats
·Integrated IEEE 802.3 ENDEC
·Complete address filtering for up to 16 physical and/or multicast addresses
·32-bit general-purpose timer
·Full-duplex loopback diagnostics
·Fabricated in low-power CMOS
·132 PQFP package
·Full network management facilities support the 802.3 layer management standard
·Integrated support for bridge and repeater applications



Specifications

If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply Voltage (VCC) ................................-0.5V to 7.0V
DC Input Voltage (VIN) ....................-0.5V to VCC+ 0.5V
DC Output Voltage (VOUT) ...............-0.5V to VCC+0.5V
Storage Temperature Range (TSTG) .......-65 to 150
Power Dissipation (PD).................................... 500 mW
Lead Temp. (TL) (Soldering, 10 sec.) ...................260
ESD Rating
(RZAP e 1.5k, CZAP e 120 pF)............................. 1.5 kV



Description

The SONIC (Systems-Oriented Network Interface Controller) is a second-generation Ethernet Controller designed to meet the demands of today's high-speed 32- and 16-bit systems. Its system interface operates with a high speed DMA that typically consumes less than 3% of the bus bandwidth (25 MHz bus clock). Selectable bus modes provide both big and little endian byte ordering and a clean interface to standard microprocessors. The linked-list buffer management system of DP83932C-25 offers maximum flexibility in a variety of environments from PC-oriented adapters to high-speed motherboard designs. Furthermore, the SONIC integrates a fully-compatible IEEE 802.3 Encoder/Decoder (ENDEC) allowing for a simple 2-chip solution for Ethernet when the SONIC is paired with the DP8392 Coaxial Transceiver Interface or a 10BASE-T transceiver.

For increased performance, the DP83932C-25 implements a unique buffer management scheme to efficiently process, receive and transmit packets in system memory. No intermediate packet copy is necessary. The receive buffer management uses three areas in memory for (1) allocating additional resources, (2) indicating status information, and (3) buffering packet data. During reception, the DP83932C-25 stores packets in the buffer area, then indicates receive status and  control information in the descriptor area. The system allocates more memory resources to the SONIC by adding descriptors to the memory resource area. The transmit buffer management uses two areas in memory: one for indicating status and control information and the other for fetching packet data. The system can create a transmit queue allowing multiple packets to be transmitted from a single transmit command. The packet data can reside on any arbitrary byte boundary and can exist in several non-contiguous locations.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Semiconductor Modules
Prototyping Products
DE1
Boxes, Enclosures, Racks
Optoelectronics
View more