DS1747

` Integrated NV SRAM, Real-Time Clock (RTC), Crystal, Power-Fail Control Circuit, and Lithium Energy Source
` Clock Registers are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations.
` Century Byte Register (Y2K Compliant)
` Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power
` BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100
` Battery Voltage-Level Indicator Flag
` Power-Fail Write Protection Allows for ±10% V<sub>CC</sub> Power-Supply Tolerance
` Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time
` DIP Module Only: Standard JEDEC Byte-Wide 512k x 8 Static RAM Pinout
` PowerCap^(R) Module Board Only: Surface-Mountable Package for Direct  onnection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-On Reset Output Pin-for-Pin Compatible with Other Densities of DS174xP Timekeeping RAM
` Also Available in Industrial Temperature Range: -40 to +85

The DS1747 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 512k x 8 nonvolatile static RAM. User access to all registers within the DS1747 is accomplished with a byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1747 also contains its own power-fail circuitry that deselects the device when the V_CC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low V_CC as errant access and update cycles are avoided.