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Part Number: DS21372T

 

 

 

 

Description: The DS21372T belongs to DS21372 Bit Error Rate Tester (BERT) family which is a software programmable t...


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DS21372T General Description


The DS21372T belongs to DS21372 Bit Error Rate Tester (BERT) family which is a software programmable test pattern generator, receiver, and analyzer capable of meeting the most stringent error performance requirements of digital transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive) conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and control interface. In addition, the DS21372 can insert single or 10 -1 to 10 -7 bit errors to verify equipment operation and connectivity. The DS21372 can be programmed to generate any pseudorandom pattern with length up to 2 32 -1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional- T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. The DS21372 user-programmable pattern registers provide the unique ability to generate loopback patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. The DS21372 operates at clock rates ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs, Routers, Bridges, CSUs, DSUs, and CPE equipment. Hence the DS21372 can initiate the loopback, run the test, check for errors, and finally deactivate the loopback.

The features of DS21372T can be summarized as (1)generates/detects digital bit patterns for analyzing, evaluating and troubleshooting digital communications systems; (2)operates at speeds from DC to 20 MHz; (3)programmable polynomial length and feedback taps for generation of any other pseudorandom pattern up to 32 bits in length including: 2 6 -1, 2 9 -1, 2 11 -1, 2 15 -1, 2 20 -1, 2 23 -1, and 2 32 -1; (4)programmable user-defined pattern and length for generation of any repetitive pattern up to 32 bits in length; (5)large 32-bit error count and bit count registers; (6)software programmable bit error insertion; (7)fully independent transmit and receive sections; (8)8-bit parallel control port; (9)detects test patterns with bit error rates up to 10 -2.

The absolute maximum ratings of DS21372T are (1)voltage on any pin relative to ground: -1.0V to +7.0V; (2)operating temperature for DS21372TN: -40°C to +85°C; (3)storage temperature: -55°C to +125°C; (4)soldering temperature: See J-STD-020A( This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.).

DS21372T datasheet

DS21372T
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