Features: 5-bit LVDS parallel data interface
Programmable Receive Equalization
Selectable DC-balance decoder
Selectable De-scrambler
Remote Sense for automatic detection and negotiation of
link status
No external receiver reference clock required
LVDS parallel interface
Programmable LVDS output clock delay
Supports output data-valid signaling
Supports keep-alive clock output
On chip LC VCOs
Redundant serial input (ELX device only)
Retimed serial output (ELX device only)
Configurable PLL loop bandwidth
Configurable via SMBus
Loss of lock and error reporting
48-pin LLP package with exposed DAPApplication Imaging: Industrial, Medical Security, Printers
Displays: LED walls, Commercial
Video Transport
Communication Systems
Test and Measurement
Industrial BusPinout
Specifications
| Function |
Deserializer |
| Total Throughput |
3125 Mbps |
| Payload/Channel |
3125 Mbps |
| Signal Conditioning |
Equalizer |
| Clock Min |
125 MHz |
| Clock Max |
312.5 MHz |
| Input Compatibility |
CML |
| Output Compatibility |
LVDS |
| Reference Clock Req'd Deserializer |
No |
| Reach |
20 meters CAT6 |
| Other Supply |
2.5 |
| SupplyVoltage |
3.3 Volt |
| ESD |
8 kV |
| Temperature Min |
-40 deg C |
| Temperature Max |
85 deg C |
| Compression Ratio |
5:1 DDR |
| Number Receivers |
1 |
| Communications |
Yes |
| Sensing & Imaging |
Yes |
| Parallel Bus Width |
5 bits |
| View Using Catalog |
Supply Voltage (VDD33) −0.3V to +4V
Supply Voltage (VDD25) -0.3V to +3.0V
LVCMOS Input Voltage −0.3V to (VDD33 + 0.3V)
LVCMOS Output Voltage -0.3V to (VDD33 + 0.3V)
CML Input/Output Voltage -0.3V to 3.6V
LVDS Output Voltage -0.3V to +3.6V
Junction Temperature+125
Storage Temperature Range−65 to +150
Lead Temperature Range
Soldering (4 sec.) +260
Package Thermal Resistance
JA +25.0/W
ESD Susceptibility
HBM 8 kVDescriptionThe DS32EL0124/ DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.
Design Tools
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DS32EL0124 Data Sheet
