DS90CF384

The DS90C383 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CF384 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 65 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughputs is 227 Mbytes/sec. The transmitter is offered with programmable edge data strobes for convenient interface with a variety of graphics controllers. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge transmitter will inter-operate with a Falling edge receiver (DS90CF384) without any translation logic. Both devices are also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint compared to the TSSOP package.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

Reliability Metrics

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Part Number	Process	EFR Reject	EFR Sample Size	PPM	LTA Rejects	LTA Device Hours	FITS	MTTF (Hours)
DS90CF384MTD	.35	0	18700	0	0	1290000	3	366041022
DS90CF384MTDX	.35	0	18700	0	0	1290000	3	366041022

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.

Design Tools

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Title	Size in Kbytes	Date
Evaluation Kit for FPD-Link Family of Serializer and Deserializer LVDS Devices			View

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Application Notes

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Title	Size in Kbytes	Date
AN-1085: Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines	304 Kbytes	4-Oct-04	Download
AN-1085 (Japanese): Application Note 1085 FPD-Link PCB and Interconnect Design-In Guidelines	192 Kbytes

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More Application Notes

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Title	Size in Kbytes	Date
AN-1127: Application Note 1127 LVDS Display Interface (LDI) TFT Data Mapping for Interoperability with FPD-Link	25 Kbytes	4-Oct-04	Download
AN-1163: Application Note 1163 TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map	13 Kbytes	15-May-04	Download

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