DS90LV001

Features:

·Single +3.3 V Supply
·LVDS receiver inputs accept LVPECL signals
·TRI-STATE outputs
·Receiver input threshold < ±100 mV
·Fast propagation delay of 1.4 ns (typ)
·Low jitter 800 Mbps fully differential data path
·100 ps (typ) of pk-pk jitter with PRBS = 2²³−1 data pattern at 800 Mbps
·Compatible with ANSI/TIA/EIA-644-A LVDS standard
·8 pin SOIC and space saving (70%) LLP package
·Industrial Temperature Range


Pinout




Specifications

Supply Voltage (VCC)                                                    −0.3V to +4V
LVCMOS/LVTTL Input Voltage (EN)                  −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage (IN+, IN−)                       −0.3V to +4V
LVDS Driver Output Voltage (OUT+, OUT−)                   −0.3V to +4V
LVDS Output Short Circuit Current Continuous
Junction Temperature                                                          +150°C
Storage Temperature Range                               −65°C to +150°C
Lead Temperature Range Soldering (4 sec.)                        +260°C
M Package                                                                            726 mW
Derate M Package                                    5.8 mW/°C above +25°C
LDA Package                                                                           2.44 W
Derate LDA Package                            19.49 mW/°C above +25°C
ESD Ratings
(HBM, 1.5kW, 100pF)                                                              2.5kV
(EIAJ, 0W, 200pF)                                                                    250V


Description

The DS90LV001 LVDS-LVDS Buffer takes an LVDS input signal and provides an LVDS output signal. In many large systems, signals are distributed across backplanes, and one of the limiting factors for system speed is the 'stub length' or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS90LV001, available in the LLP (Leadless Leadframe Package) package, will allow the receiver to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range will allow the DS90LV001 to receive differential signals from LVPECL as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-LVDS translator.

An output enable pin is provided, which allows the user to place the LVDS output in TRI-STATE.

The DS90LV001 is offered in two package options, an 8 pin LLP and SOIC.