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DS90LV032A

Features: ·>400 Mbps (200 MHz) switching rates·0.1 ns channel-to-channel skew (typical)·0.1 ns differential skew (typical)·3.3 ns maximum propagation delay·3.3V power supply design·Power down high impedance on LVDS inputs·Low Power design (40mW 3.3V static)·Interoperable with existing 5V LVDS n...

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SeekIC No. : 004329398 Detail

DS90LV032A: Features: ·>400 Mbps (200 MHz) switching rates·0.1 ns channel-to-channel skew (typical)·0.1 ns differential skew (typical)·3.3 ns maximum propagation delay·3.3V power supply design·Power down hig...

DS90LV032A Data Sheet

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Part Number:
DS90LV032A
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

·>400 Mbps (200 MHz) switching rates
·0.1 ns channel-to-channel skew (typical)
·0.1 ns differential skew (typical)
·3.3 ns maximum propagation delay
·3.3V power supply design
·Power down high impedance on LVDS inputs
·Low Power design (40mW 3.3V static)
·Interoperable with existing 5V LVDS networks
·Accepts small swing (350 mV typical) VID
·Supports open, short and terminated input fail-safe
·Compatible with ANSI/TIA/EIA-644
·Industrial temp. operating range (-40°C to +85°C)
·Available in SOIC and TSSOP Packaging




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Specifications

PHY Type Receiver
Family LVDS
Channels 4 Channels
Max Data Rate 400 Mbps
Input Compatibility LVDS
Output Compatibility LVTTL
Power Consumption_ 34 mW
Special Features Failsafe
SupplyVoltage 3.3 Volt
JTAG1149.1 No
Temperature Min -40 deg C
Temperature Max 85 deg C
Function Receiver
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Description

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The receiver supports a TRI-STATE™ function that may be used to multiplex outputs. The receiver also supports open, shorted and terminated (100 Ohm) input Fail-safe. The receiver output will be HIGH for all fail-safe conditions.

The DS90LV032A and companion LVDS line driver (eg. DS90LV031A) provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

Reliability Metrics

Part Number Process EFR Reject EFR Sample Size PPM LTA Rejects LTA Device Hours FITS MTTF (Hours)
DS90LV032A MDC .35 0 18700 0 0 1290000 3 366041022
DS90LV032ATM .35 0 18700 0 0 1290000 3 366041022
DS90LV032ATMTC .35 0 18700 0 0 1290000 3 366041022
DS90LV032ATMTCX .35 0 18700 0 0 1290000 3 366041022
DS90LV032ATMX .35 0 18700 0 0 1290000 3 366041022
DS90LV032AW-MLS .35 0 18700 0 0 1290000 3 366041022
DS90LV032AW-QML .35 0 18700 0 0 1290000 3 366041022
DS90LV032AWGMLS .35 0 18700 0 0 1290000 3 366041022
DS90LV032AWGQML .35 0 18700 0 0 1290000 3 366041022

Note: The Early Failure Rates (EFR) were calculated as point estimate PPM based on rejects and sample size for EFR. The Long Term Failure Rates were calculated at 60% confidence using the Arrhenius equation at 0.7eV activation energy and derating the assumed stress temperature of 150°C to an application temperature of 55°C.

For more information on Reliability Metrics, please click here.


Application Notes

Title Size in Kbytes Date
AN-1110: Application Note 1110 LVDS Quad Dynamic I CC vs Frequency 159 Kbytes 4-Oct-04 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

Title Size in Kbytes Date
AN-971: Application Note 971 An Overview of LVDS Technology 168 Kbytes 5-Oct-98 Download
AN-971 (Japanese): Application Note 971 An Overview of LVDS Technology
640){this.height=this.height*640/this.width;this.width=640;}' border="0" alt=" Connection Diagram">		 168 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.






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