DSP56005

Features: • Efficient, object code compatible, 24-bit 56000-Family DSP engine- Up to 25 Million Instructions per Second (MIPS) 40 ns instruction cycle at 50 MHz- Up to 150 Million Operations per Second (MOPS) at 50 MHz- Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 cl...

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DSP56005 Picture
SeekIC No. : 004329611 Detail

DSP56005: Features: • Efficient, object code compatible, 24-bit 56000-Family DSP engine- Up to 25 Million Instructions per Second (MIPS) 40 ns instruction cycle at 50 MHz- Up to 150 Million Operations ...

floor Price/Ceiling Price

Part Number:
DSP56005
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/26

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Product Details

Description



Features:

• Efficient, object code compatible, 24-bit 56000-Family DSP engine
- Up to 25 Million Instructions per Second (MIPS) 40 ns instruction cycle at 50 MHz
- Up to 150 Million Operations per Second (MOPS) at 50 MHz
- Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks
- Highly parallel instruction set with unique DSP addressing modes
- Two 56-bit accumulators including extension byte
- Parallel 24*24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
- Double precision 48*48-bit multiply with 96-bit result in 6 instruction cycles
- 56-bit Addition/subtraction in 1 instruction cycle
- Fractional arithmetic with support for multiprecision arithmetic
- Hardware support for block-floating point FFT
- Hardware nested DO loops
- Zero-overhead fast interrupts (2 instruction cycles)
- Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories



Specifications

Rating
Symbol
Value
Unit
Supply Voltage
VCC
0.3 to +7.0
V
All Input Voltages
VIN
GND - 0.5 to VCC + 0.5
V
Current Drain per Pin excluding VCC and GND
I
10
mA
Operating Temperature Range
TJ
-40 to +105
°C
Storage Temperature
Tstg
55 to +150
°C



Description

The DSP56005 is an MPU-style general purpose Digital Signal Processor (DSP), composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by a large program RAM, two independent data RAMs, and two data ROMs with sine and arc-tangent tables. Like the DSP56002, the DSP56005 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), a 24-bit timer/event counter, and On-Chip Emulation (OnCE ™) port. Features of the DSP56005 include the large on-chip program memory, five Pulse Width Modulators (PWM), a watchdog timer, and an address decode pin for external peripherals. This combination of features, illustrated in Figure 1, makes the DSP56005 a cost-effective, high-performance solution for many DSP and control applications, especially in high-performance motor control, optical disk drives and audio processing.




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