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DSP56167

Features: • Digital Signal Processing Core Up to 30 Million Instructions Per Second (MIPS) at 60 MHz with 33.3 ns instruction cycle Single-cycle 16´ 16-bit parallel Multiply-Accumulate 2´ 40-bit accumulators with extension byte Fractional and integer arithmetic with support for m...

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SeekIC No. : 004329617 Detail

DSP56167: Features: • Digital Signal Processing Core Up to 30 Million Instructions Per Second (MIPS) at 60 MHz with 33.3 ns instruction cycle Single-cycle 16´ 16-bit parallel Multiply-Accumulate 2...

DSP56167 Data Sheet

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Part Number:
DSP56167
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Digital Signal Processing Core
Up to 30 Million Instructions Per Second (MIPS) at 60 MHz with 33.3 ns instruction cycle
Single-cycle 16
 
´ 16-bit parallel Multiply-Accumulate
2
 
´ 40-bit accumulators with extension byte
Fractional and integer arithmetic with support for multiprecision arithmetic
Highly parallel instruction set with unique DSP addressing modes
Nested hardware DO loops including infinite loops and DO zero loop
Two instruction LMS adaptive filter loop
Fast auto-return interrupts
Three external interrupt request pins
Three 16-bit internal data and three 16-bit internal address buses
Individual programmable wait states on the external bus for program, data, and peripheral memory spaces
Programmable absolute short addressing mode
Off-chip memory-mapped peripheral space with programmable access time and separate peripheral enable pin
Peripheral Address Generation Unit (PAGU)
On-chip memory-mapped peripheral registers
On-Chip Emulation (OnCE Ô) port for unobtrusive, processor speedindependent debugging with DR line static latch with Reset
• Memory
Modified Harvard architecture permits simultaneous accesses to program and data memories
2 K
 
´ 16-bit on-chip Program RAM
4 K
 
´ 16-bit on-chip data RAM
64
 
´ 16-bit bootstrap ROM
External memory expansion with 16-bit address and data buses with static latches with Reset and software-controlled BG pull-down
Bootstrap loading from external byte-wide Program ROM, Host Interface, or 16-bit Synchronous Serial Interface (SSI0)


Pinout

Connection Diagram


Specifications

Rating Symbol Value Unit
Supply Voltage VDD 0.3 to +7.0 V
All Input Voltages VIN (VSS 0.5) to (VDD + 0.5) V
Current Drain per Pin excluding VDD and VSS I 10 mA
Storage Temperature Tstg 55 to +150 °C



Description

The general-purpose, programmable DSP56167 is an enhanced version of the DSP56166 with added features. Designed primarily for speech coding and digital communications, the DSP56167 has a built-inSD codec and Phase Lock Loop (PLL). This MPU-style DSP also contains memories and digital peripherals that provide a cost effective, high performance solution to many DSP applications. On-Chip Emulation (OnCEä) circuitry provides convenient and inexpensive debug facilities normally available only through expensive external hardware. This RAM-based DSP contains a 2 K´ 16 Program RAM and a 4 K´ 16 data RAM. The Central Processing Unit (CPU) consists of three execution units operating in parallel allowing up to six operations to occur in an instruction cycle. This parallelism greatly increases the effective processing speed of the DSP56167. The MPU-style programming model and instruction set allow straightforward generation of efficient, compact code. The DSP56167 is a member of Motorola's DSP56100 family of 16-bit Digital Signal Processors (DSPs).




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