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DSP56652

Features: RISC M¥CORE MCU· 32-bit load/store RISC architecture· Fixed 16-bit instruction length· 16-entry 32-bit general-purpose register file· 32-bit internal address and data buses· Efficient four-stage, fully interlocked execution pipeline· Single-cycle execution for most instructions, two ...

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SeekIC No. : 004329630 Detail

DSP56652: Features: RISC M¥CORE MCU· 32-bit load/store RISC architecture· Fixed 16-bit instruction length· 16-entry 32-bit general-purpose register file· 32-bit internal address and data buses· Efficient ...

DSP56652 Data Sheet

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Part Number:
DSP56652
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/18

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Product Details

Description



Features:

RISC M¥CORE MCU
· 32-bit load/store RISC architecture
· Fixed 16-bit instruction length
· 16-entry 32-bit general-purpose register file
· 32-bit internal address and data buses
· Efficient four-stage, fully interlocked execution pipeline
· Single-cycle execution for most instructions, two cycles for branches and memory accesses
·Special branch, byte, and bit manipulation instructions
· Support for byte, half-word, and word memory accesses
· Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register file
High Performance DSP56600 Core
· 1×engine (e.g., 70 MHz = 70 MIPS)
· Fully pipelined 16×16-bit parallel multiplier-accumulator (MAC)
· Two 40-bit accumulators including extension bits
· 40-bit parallel barrel shifter
·Highly parallel instruction set with unique DSP addressing modes
· Position-independent code support
· Nested hardware DO loops
· Fast auto-return interrupts
· On-chip support for software patching and enhancements
·Realtime trace capability via address bus visibility mode
On-chip Memories
· 4K×32-bit MCU ROM
· 512×32-bit MCU RAM
·48K×24-bit DSP program ROM
· 512×24-bit DSP program RAM
· 20K×16-bit DSP data ROM, split into 10K x 16-bit each of X and Y data ROM spaces
· 14K×16-bit DSP data RAM, split into (7 + 1)K×16-bit X data RAM and 6K x 16-bit Y data RAM spaces
On-chip Peripherals
· Fully programmable phase-locked loop (PLL) for DSP clock generation
· External interface module (EIM) for glueless system integration
· External 22-bit address and 16-bit data MCU buses
· Thirty-two source MCU interrupt controller
· Intelligent MCU/DSP interface (MDI) dual 1K x 16-bit RAM (shares 1K DSP X data RAM) with messaging status and control
· Serial audio codec port
· Serial baseband codec port
· Protocol timer frees the MCU from radio channel timing events
· Queued serial peripheral interface (SPI)
· Keypad port capable of scanning up to an 8×8 matrix keypad
· General-purpose MCU and DSP timers
· Pulse width modulation output
· Universal asynchronous receiver/transmitter (UART) with FIFO
· IEEE 1149.1-compliant boundary scan JTAG Test access port (TAP)
· Integrated DSP/M¥CORE On-Chip Emulation (OnCEª) module
· DSP address bus visibility mode for system development
· ISO 7816-compatible Smart Card port Operating Features:
· Comprehensive static and dynamic power management
· M¥CORE operating frequency: dc to 16.8 MHz at 1.8 V
· DSP operating frequency: dc to 58.8 MHz at 1.8 V
· Internal operating voltage range: 1.8Ð2.5 V with 3.3 V-tolerant I/O
· Operating temperature: Ð40û to 85ûC ambient
· Package option: 15×15 mm, 196-lead PBGA


Application

The DSP56652 is intended for use in cellular subscriber applications and other applications needing both DSP and control processing.


Specifications

Rating
Symbol
Value
Unit
Internal supply voltage
VCCI
-0.3 to +2.75
V
External supply voltage
VCCE
-0.3 to +3.6
V
Operating temperature range
TA
-40 to +85
°C
Storage temperature
TSTG
-55 to +125
°C



Description

The following section provides information about the available packages for this product DSP56652, including diagrams of the package pinouts and tables describing how the signals of the DSP 56652 are allocated for the 196-pin Plastic ball grid array (PBGA) package. Top and bottom views of the PBGA package are shown in Figure 1-1 and Figure 1-2 on page 1-3 with their pin-outs, while Table 1-1 on page 1-4 identifies the signal associated with each pin.




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