Features: • Efficient 16-bit DSP56800 Family DSP engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique DSP addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE Debug Programming InterfacePinout
Specifications
| Characteristic |
Symbol |
Min |
Max |
Unit |
| Supply voltage, core |
VDD |
VSS 0.3 |
VSS + 3.0 |
V |
Supply voltage, IO
Supply voltage, Analog |
VDDIO
2
VDDA
2 |
VSSIO 0.3
VSSIO 0.3 |
VSSIO + 4.0
VSSA + 4.0 |
V |
Digital input voltages
Analog input voltages - XTAL, EXTAL |
VIN
VINA |
VSSIO 0.3
VSSIO 0.3 |
VSSIO + 5.5
VSSA + 3.0 |
V |
Current drain per pin excluding VDD, VSS, VDDA, VSSA,
VDDIO, VSSIO |
I |
|
10 |
mA |
| Junction temperature |
TJ
|
|
150 |
°C |
| Storage temperature |
TSTG |
55 |
150 |
°C |
1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5VDescriptionDigital Signal Controller
The DSP56F826 is a member of the DSP56800 core-based family of Digital Signal Processors (DSPs). It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution for general purpose applications. Because of its low cost, configuration flexibility, and compact program code, the DSP56F826 is wellsuited for many applications. The DSP56F826 includes many peripherals that are especially useful for applications such as: noise suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic alarms, POS terminals, feature phones.
The DSP56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications.
The DSP56F826 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The DSP56F826 also provides two external dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.
The DSP56F826 DSP controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It also supports program execution from external memory.
The DSP56F826 incorporates a total of 2K words of BootFLASH for easy customer-inclusion of fieldprogrammable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page sizes of 256 words. The BootFLASH memory can also be either bulk- or page-erased.
This DSP controller also provides a full set of standard programmable peripherals including one Synchronous Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and quad timer can be used as General Purpose Input/Outputs (GPIOs) if a timer function is not required.
DSP56F826 Data Sheet
