EDI2GG464128V

Features: · 4x128Kx64 Synchronous· Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns· Flow-Through Architecture· Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#)· Clock Controlled Registered Address· Clock Controlled Registered Global Write (GW#)· Aysnchronous Output Enable (G#)· ...

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SeekIC No. : 004333839 Detail

EDI2GG464128V: Features: · 4x128Kx64 Synchronous· Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns· Flow-Through Architecture· Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#)· Clock Controlled Reg...

floor Price/Ceiling Price

Part Number:
EDI2GG464128V
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

· 4x128Kx64 Synchronous
· Access Speed(s): TKHQV = 9.5, 10, 11, 12, 15ns
· Flow-Through Architecture
· Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#)
· Clock Controlled Registered Address
· Clock Controlled Registered Global Write (GW#)
· Aysnchronous Output Enable (G#)
· Internally self-timed Write
· Gold Lead Finish
· 3.3V +10%, -5% Operation
· Access Speed(s): tKHQV = 9.5, 10, 11, 12, 15ns
· Common Data I/O
· High Capacitance (30pf) drive, at rated Access Speed
· Single total array Clock
· Multiple Vcc and GND



Pinout

  Connection Diagram


Specifications

Voltage on Vcc Relative to Vss -0.5V to +4.6V
VIN -0.5V to Vcc +0.5V
Storage Temperature -55°C to +125°C
Operating Temperature (Commercial) 0°C to +70°C
Operating Temperature (Industrial) -40°C to +85°C
Short Circuit Output Current 20 mA



Description

The EDI2KG64128VxxD is a Synchronous SRAM, 60 position Card Edge DIMM (120 contacts) Module, or ga nized as 4x128Kx64. The Module con tains eight (8) Syn chro nous Burst Ram Devices, packaged in the in dus try standard JEDEC 14mmx20mm TQFP placed on a Mul ti lay er FR4 Sub strate. The module architecture is defi ned as a Synchronous Only, Flow-Through, Early Write Device. This module provides High Performance, Ultra Fast access times at a cost per bit benefi t over BiCMOS Asynchronous SRAM based devices. As well as improved cost per bit, the use of Synchronous or Synchronous Burst devices or modules can ease the memory subsystem design by reducing or easing the memory controller requirement.

EDI2KG64128VxxD Synchronous operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output enable. All read and write operations to this module are performed on Quad Words (64 bit op er a tions).

Write cycles are internally self timed and are initiated by a rising clock edge. This feature relieves the designer the task of developing external write pulse width cir cuit ry.




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