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EDS2508APTA-TI

Features: • 3.3V power supply• Clock frequency: 133MHz (max.)• LVTTL interface• Single pulsed /RAS• 4 banks can operate simultaneously and independently• Burst read/write operation and burst read/single write operation capability• Programmable burst length...

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SeekIC No. : 004333890 Detail

EDS2508APTA-TI: Features: • 3.3V power supply• Clock frequency: 133MHz (max.)• LVTTL interface• Single pulsed /RAS• 4 banks can operate simultaneously and independently• Burst re...

EDS2508APTA-TI Data Sheet

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Part Number:
EDS2508APTA-TI
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
-Sequential (BL = 1, 2, 4, 8)
-Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS2504/08AP)
: UDQM, LDQM (EDS2516AP)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
-Auto refresh
-Self refresh
• Ambient temperature range: 40 to +85°C


Pinout

Connection Diagram


Specifications

Parameter

Symbol

Rating

Unit

Voltage on any pin relative to VSS
VT
0.5 to VDD + 0.5 ( 4.6 (max.))
V
Supply voltage relative to VSS
VDD
0.5 to +4.6
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating temperature
TA
40 to +85
°C

Storage temperature
Tstg
55 to +125
°C

Notes: 1. Respect to VSS.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.




Description

The EDS2504AP is a 256M bits SDRAM organized as 16,777,216 words × 4 bits × 4 banks. The EDS2508 AP is a 256M bits SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDS2516 AP is a 256M bits SDRAM organized as 4194304 words × 16 bits × 4 banks. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54- pin plastic TSOP (II).




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