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EDX5116ABSE

Features: ·Highest pin bandwidth available 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling·Bi-directional differential RSL (DRSL)- Flexible read/write bandwidth allocation- Minimum pin count·On-chip termination-Adaptive impedance matching-Reduced system cost and routing complexity·Highest sust...

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SeekIC No. : 004333927 Detail

EDX5116ABSE: Features: ·Highest pin bandwidth available 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling·Bi-directional differential RSL (DRSL)- Flexible read/write bandwidth allocation- Minimum pin count·On-...

EDX5116ABSE Data Sheet

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Part Number:
EDX5116ABSE
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

· Highest pin bandwidth available 4000/3200/2400 Mb/s Octal Data Rate (ODR) Signaling
· Bi-directional differential RSL (DRSL)
- Flexible read/write bandwidth allocation
- Minimum pin count
· On-chip termination
-Adaptive impedance matching
-Reduced system cost and routing complexity
· Highest sustained bandwidth per DRAM device
· 8000/6400/4800 MB/s sustained data rate
· Eight banks: bank-interleaved transactions at full bandwidth
· Dynamic request scheduling
· Early-read-after-write support for maximum efficiency
· Zero overhead refresh
· Dynamic width control
·EDX5116ABSE supports × 16, × 8 and × 4 mode
· Low latency
· 2.0/2.5/3.33 ns request packets
· Point-to-point data interconnect for fastest possible flight time
· Support for low-latency, fast-cycle cores


Pinout

Connection Diagram


Description

The EDX5116ABSE is a 512M bits XDRTM DRAM organized as 32M words * 16 bits. It is a general-purpose high-performance memory device suitable for use in a broad range of applications.

The use of Differential Rambus Signaling Level (DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies. XDR DRAM devices are capable of sustained data transfers of 8000/6400/4800 MB/s.

XDR DRAM device EDX5116ABSE architecture allows the highest sustained bandwidth for multiple, interleaved randomly addressed memory transactions. The highly-efficient protocol yields over 95% utilization while allowing fine access granularity. The devices eight banks support up to four interleaved transactions. It is packaged in 104-ball FBGA (BGA®) compatible with Rambus XDR DRAM pin configuration.




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