EN25P64

The EN25P64 is a 64M-bit (8192K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.The EN25P64 is designed to allow either single Sector/Block at a time or full chip erase operation. The EN25P64 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector or block.

Features of the EN25P64 are:(1)lockable 512byte OTP security sector; (2)minimum 100K endurance cycle; (3)industrial temperature range; (4)write protect all or portion of memory via software; (5)enable/disable protection with WP# pin; (6)uniform sector architecture:- one hundred twenty-eight 64-Kbyte sectors.The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress.

The absolute maximum ratings of the EN25P64 can be summarized as:(1)storage temperature:-65 to 150;(2)plastic packages:-65 to 125;(3)output short circuit current:200mA;(4)input and output voltage:-0.5 to 4.0 V;(5)Vcc:-0.5 to 4.0V.Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability.The device is first selected by driving Chip Select Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output , each bit being shifted out during the falling edge of Serial Clock .The instruction sequence is shown in Figure 18. The Read Identification (RDID) instruction is terminated by driving Chip Select High at any time during data output.