EP1S10

Features: ·10,570 to 79,040 LEs; see Table1-1· Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources·TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers ·High-speed DSP blocks provide dedicate...

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SeekIC No. : 004337008 Detail

EP1S10: Features: ·10,570 to 79,040 LEs; see Table1-1· Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources·TriMatrixTM memory consisting of three RAM block sizes to implement...

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Part Number:
EP1S10
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/29

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Product Details

Description



Features:

·10,570 to 79,040 LEs; see Table1-1
· Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources
·TriMatrixTM  memory consisting of three RAM block sizes to  implement true dual-port memory and first-in first-out (FIFO)  buffers
·High-speed DSP blocks provide dedicated implementation of  multipliers (faster than 300MHz), multiply-accumulate functions,  and finite impulse response (FIR) filters
· Up to 16 global clocks with 22 clocking resources per device region Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switch- over, real-time PLL reconfiguration, and advanced multiplication  and phase shifting
·Support for numerous single-ended and differential I/O standards
·High-speed differential I/O support on up to 116 channels with up  to 80channels optimized for 840 megabits per second (Mbps)
·Support for high-speed networking and communications bus  standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM    technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),  and SFI-4
·Differential on-chip termination support for LVDS
·Support for high-speed external memory, including zero bus  turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM),  and single data rate (SDR) SDRAM
·Support for 66-MHz PCI (64 and 32bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster  speed-grade devices
·Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices
·Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices
·Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices
·Support for multiple intellectual property megafunctions from Altera MegaCore  functions and Altera Megafunction Partners  megafunctions Program (AMPPSM
· Support for remote configuration updates




Description

Stratix  devices EP1S10 contain a two-dimensional row- and column-based  architecture to implement custom logic. A series of column and row  interconnects of varying length and speed provide signal interconnects  between logic array blocks (LABs), memory block structures, and DSP  blocks.

The EP1S10 logic array consists of LABs, with 10 logic elements (LEs) in each  LAB. An LE is a small unit of logic providing efficient implementation o user logic functions. LABs are grouped into rows and columns across th device.

EP1S10 M512 RAM blocks are simple dual-port memory blocks with 512 bits plu parity (576 bits). These blocks provide dedicated simple dual-port or  single-port memory up to 18-bits wide at up to 318MHz. M512 blocks ar grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus  parity (4,608 bits). These blocks provide dedicated true dual-port, simpl dual-port, or single-port memory up to 36-bits wide at up to 291MHz.  These blocks are grouped into columns across the device in between  certain LABs.

EP1S10 M-RAM blocks are true dual-port memory blocks with 512Kbits plus  parity (589,824bits). These blocks provide dedicated true dual-port,  simple dual-port, or single-port memory up to 144-bits wide at up to 269MHz. Several M-RAM blocks are located individually or in pairs within the device!s logic array Digital signal processing (DSP) blocks can implement up to either eight full-precision 9!á9-bit multipliers four full-precision 18 !á 18-bit multipliers, or one full-precision 36!á36-bit mutiplier with add or  subtract features. These blocks also contain 18-bit input shift registers fo digital signal processing applications, including FIR and infinite impuls response (IIR) filters. DSP blocks are grouped into two columns in each  device.

Each EP1S10 Stratix device I/O pin is fed by an I/O element (IOE) located at th end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards.

Each EP1S10 IOE contains a bidirectional I/O buffer and six registers for  registering input, output, and output-enable signals. When used with




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