EP201

Features: • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.• Automatic bus arbitration for address bus and data bus based on internal bus request.• Separate address bus and data bus tenure with individual grant signals.• Supports...

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SeekIC No. : 004337010 Detail

EP201: Features: • Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.• Automatic bus arbitration for address bus and data bus based on internal bus req...

floor Price/Ceiling Price

Part Number:
EP201
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/26

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Product Details

Description



Features:

• Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.
• Automatic bus arbitration for address bus and data bus based on internal bus request.
• Separate address bus and data bus tenure with individual grant signals.
• Supports address bus retry and data transfer error.
• Qualified address bus grant and data bus grant through the use of bus busy signals.
• User specified burst data transfer and single beat data transfer.
• Supports two back-end user request ports with built-in arbitration.
• Efficient back-end bus for internal data transfer.
• Supports bus parking.
• Designed for ASIC or programmable logic device implementations in various system environments.
• Fully static design with edge triggered flip-flops.
• Optimized for Actel SX-A, RTSX-S, AX, and APA product families.



Description

The EP201 PowerPC bus master is a bus interface unit designed for the PowerPC host bus. It allows the user to initiate data transfer directly on the PowerPC CPU bus through a very simple user interface. The PowerPC bus master arbitrates for the PowerPC address bus before starting any transfers. It handles separate address and data bus tenure so that data bus is arbitrated independently from the address bus. The EP201 bus master handles address retry by the CPU or other sources on the CPU bus. Upon address retry, it automatically re-starts the data transfer unless an error has occurred. Single beat, burst data and extended MPC8260 data transfer are supported. Different data size and transfer types are allowed and can be specified through an internal back-end bus. There are two user interface ports provided by the bus master. It allows two different devices to access the PowerPC bus through a single bus master. The EP201 bus master contains arbitration logic to arbitrate between the two request ports.




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