EP312

`High-performance EPLDs with 12 macrocells (EP312) or 24 macrocells (EP324)
Combinatorial speeds as fast as 25 ns
Counter frequencies of up to 33.3 MHz
Pipelined data rates of up to 66 MHz
`Multiple 20-pin PAL and GAL replacement and integration
`Device erasure and reprogramming with advanced, nonvolatile EPROM configuration elements
`Programmable registers providing D, T, JK, and SR flipflops with individual Clear and Clock controls
`Dual feedback on all macrocells for implementing buried registers with bidirectional I/O
`Programmable-AND /allocatable-OR structure allowing up to 16 product terms per macrocell
`Two product terms on all macrocell control signals
`Programmable inputs (8 in EP312, 10 in EP324) configurable as latches, registers, or flow-through input
`Available in windowed ceramic and one-time-programmable (OTP) plastic packages with 24 to 44 pins:
24-pin ceramic and plastic dual in-line package (CerDIP and PDIP)
28-pin plastic J-lead chip carrier (PLCC)
40-pin CerDIP and PDIP
44-pin PLCC
`One gl obal Clock pin; one global Input Latch Enable/Input Clock/Input (ILE /ICLK /INPUT ) pin
`Programmable "standby" option for low-power operation
`Programmable Security Bit for total protection of proprietary designs
`100% generically testable to provide 100% programming yield
`Software design support with the Altera PLDshell Plus software and a wide range of third-party tools; programming support through third-party vendors