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MFG:ALTERA  Package Cooled:BGA  D/C:06+  

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Part Number: EPM7256AE

 

MFG: ALTERA

Package Cooled: BGA

D/C: 06+

Description: MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera's s...


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EPM7256AE General Description


MAX 7000A (including MAX 7000AE) devices are high-density, highperformance devices based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROMbased MAX 7000A devices operate with a 3.3-V supply voltage and provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5, -6, -7 and some -10 speed grades are compatible with the timing requirements for 33 MHz operation of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 . See Table 2.

EPM7256AE Maximum Ratings

Symbol
Parameter
Conditions
Min
Max
Unit
VCC
Supply voltage
With respect to ground (2)
-0.5
4.6
V
VI
DC input voltage
-2.0
5.75
V
IOUT
DC output current, per pin
-25
25
mA
TSTG
Storage temperature
No bias
-65
150
° C
TA
Ambient temperature
Under bias
-65
135
° C
TJ
Junction temperature
BGA, FineLine BGA, PQFP, and
TQFP packages, under bias
135
° C

EPM7256AE Features

High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX® ) architecture (see    Table 1)
3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
Enhanced ISP features
    Enhanced ISP algorithm for faster programming (excluding EPM7128A and EPM7256A devices)
    ISP_Done bit to ensure complete programming (excluding EPM7128A and EPM7256A devices)
    Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz

EPM7256AE Connection Diagram

EPM7256AE  Connection Diagram

EPM7256AE datasheet

EPM7256AE
PDF/DataSheet Download

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