EPM7256AETC144-10N

The EPM7256AETC144-10N is one member of the EPM7256AE family which is designed as the high-density, highperformance device that provides programmable speed/power optimization. It contains from 32 to 512 macrocells that are combined into groups of 16 macrocells, called logic array blocks (LABs). Each macrocell has a programmable-AND/fixed-OR array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. Also it is supported by Altera development systems, which are integrated packages that offer schematic, text-including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)-and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming.

Features of the EPM7256AETC144-10N are:(1)Built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1;(2)Supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71;(3)Pin-compatible with the popular 5.0-V MAX 7000S devices;(4)High-density PLDs ranging from 600 to 10,000 usable gates;(5)Extended temperature range;(6)Programmable interconnect array (PIA) continuous routing structure for fast, predictable performance;(7)PCI-compatible;(8)Bus-friendly architecture, including programmable slew-rate control;(9)Open-drain output option;(10)Programmable macrocell registers with individual clear, preset, clock, and clock enable controls.

The absolute maximum ratings of the EPM7256AETC144-10N can be summarized as:(1)Supply voltage:0.5 to 4.6 V;(2)DC input voltage:2.0 to 5.75 V;(3)DC output current, per pin:25 to 25 mA;(4)Storage temperature:65 to 150 °C;(5)Ambient temperature:65 to 135 °C;(6)Junction temperature: 135 °C. If you want to know more information such as the electrical characteristics about the EPM7256AETC144-10N, please download the datasheet in www.seekic.com or www.chinaicmart.com.