Features: • Low power consumption• 20 MHz to 85 MHz shift clock support• 50% duty cycle on the clock output of receiver• ±1V common-mode range around 1.2V• Narrow bus reduces cable size and cost• High throughput (up to 1.785 Gbps throughput)• Up to 595 Mbp...
FIN1217: Features: • Low power consumption• 20 MHz to 85 MHz shift clock support• 50% duty cycle on the clock output of receiver• ±1V common-mode range around 1.2V• Narrow bus r...
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The FIN1217 and FIN1215 transform 21-bit wide parallel LVTTL (Low Voltage TTL) data into 3 serial LVDS (Low Voltage Differential Signaling) data streams. A phaselocked transmit clock of FIN1217 and FIN1215 is transmitted in parallel with the data stream over a separate LVDS link. Every cycle of transmit clock 21 bits of input LVTTL data are sampled and transmitted.
The FIN1218 and FIN1216 receive and convert the 3 serial LVDS data streams back into 21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and Deserializers available. For the FIN1217, at a transmit clock frequency of 85 MHz, 21 bits of LVTTL data are transmitted at a rate of 595 Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces.