FLEX10K

Features:

`The industry's first embedded programmable logic device (PLD) family, providing System-on-a-Programmable-Chip TM integration
Embedded array for implementing megafunctions, such as efficient memory and specialized logic functions
Logic array for general logic functions
`High density
10,000 to 250,000 typical gates (see Tables 1 and 2)
Up to 40,960 RAM bits; 2,048 bits per embedded array block (EAB), all of which can be used without reducing logic capacity
`System-level features
MultiVolt<sup>TM</sup>I/O interface support
5.0-V tolerant input pins in FLEX®10KA devices
Low power consumption (typical specification less than 0.5 mA in standby mode for most devices)
FLEX 10K and FLEX 10KA devices support peripheral component interconnect Special Interest Group (PCI SIG) PCI
`Local Bus Specification, Revision 2.2
FLEX 10KA devices include pull-up clamping diode, selectable on a pin-by-pin basis for 3.3-V PCI compliance
Select FLEX 10KA devices support 5.0-V PCI buses with eight fewer loads
Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming any device logic


Pinout




Specifications

Symbol	Parameter	Conditions	Min	Max	Unit
VCC	Supply voltage	With respect to ground (2)	2.0	7.0	V
VI	DC input voltage		2.0	7.0	V
IOUT	DC output current, per pin		25	25	mA
TSTG	Storage temperature	No bias	65	150	° C
TAMB	Ambient temperature	Under bias	65	135	° C
TJ	Junction temperature	Ceramic packages, under bias		150	° C
		PQFP, TQFP, RQFP, and BGA packages, under bias		135	° C

Description

Altera's FLEX 10K devices are the industry's first embedded PLDs. Based on reconfigurable CMOS SRAM elements, the Flexible Logic Element MatriX (FLEX) architecture incorporates all features necessary to implement common gate array megafunctions. With up to 250,000 gates, the FLEX 10K family provides the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.

FLEX 10K devices are reconfigurable, which allows 100% testing prior shipment. As a result, the designer is not required to generate test vectors for fault coverage purposes. Additionally, the designer does not need to manage inventories of different ASIC designs; FLEX 10K devices can be configured on the board for the specific functionality required.

Table 6 shows FLEX 10K performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. No special design technique was required to implement the applications; the designer simply inferred or instantiated a function in Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), schematic design file.