FLEX10KE

Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
    Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
    Dual-port capability with up to 16-bit width per embedded array block (EAB)
    Logic array for general logic functions
High density
    30,000 to 200,000 typical gates (see Tables 1 and 2)
    Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
System-level features
    MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
    Low power consumption
    Bidirectional I/O performance (t_SU and t_CO) up to 212 MHz
    Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
    -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
    Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic
    Fabricated on an advanced process and operate with a 2.5-V internal supply voltage
    In-circuit reconfigurability (ICR) via external configuration devices, intelligent controller, or JTAG port
    ClockLockTM and ClockBoostTM options for reduced clock delay/skew and clock multiplication
    Built-in low-skew clock distribution trees
    100% functional testing of all devices; test vectors or scan chains are not required
    Pull-up on I/O pins before and during configuration
Flexible interconnect
    FastTrack^® Interconnect continuous routing structure for fast, predictable interconnect delays
    Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)
    Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)
     Tri-state emulation that implements internal tri-state buses
     Up to six global clock signals and four global clear signals
Powerful I/O pins
    Individual tri-state output enable control for each pin
    Open-drain option on each I/O pin
    Programmable output slew-rate control to reduce switching noise
    Clamp to V_CCIO user-selectable on a pin-by-pin basis
    Supports hot-socketing
Software design support and automatic place-and-route provided by Altera's development systems for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800
Flexible package options
    Available in a variety of packages with 144 to 672 pins, including the innovative FineLine BGATM packages (see Tables 3 and 4)
    SameFrameTM pin-out compatibility between FLEX 10KA and FLEX 10KE devices across a range of device densities and pin counts
Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), DesignWare components, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, VeriBest, and Viewlogic

Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices. Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions. With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.

The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification. FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.

Table 5 shows FLEX 10KE performance for some common designs. All performance values were obtained with Synopsys DesignWare or LPM functions. Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or schematic design file.