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Part Number: GAL16LV8

 

 

 

 

Description: The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance availa...


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GAL16LV8 General Description


The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.

The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations.

Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

GAL16LV8 Maximum Ratings

Supply voltage VCC ................................... 0.5 to +4.6V
Input voltage applied ................................ 0.5 to +5.6V
I/O voltage applied ................................... 0.5 to +4.6V
Off-state output voltage applied ............... 0.5 to +4.6V
Storage Temperature ................................. 65 to 150
Ambient Temperature with
   Power Applied ......................................... 55 to 125

1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to
   the device. These are stress only ratings and functional operation of the device at these or at any other
   conditions above those indicated in the operational sections of this specification is not implied (while
   programming, follow the programming specifications).


GAL16LV8 Features

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
   - 3.5 ns Maximum Propagation Delay
   - Fmax = 250 MHz
   - 2.5 ns Maximum from Clock Input to Data Output
   - UltraMOS® Advanced CMOS Technology
• 3.3V LOW VOLTAGE 16V8 ARCHITECTURE
   - JEDEC-Compatible 3.3V Interface Standard
   - 5V Compatible Inputs
   - I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
• ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
• E2 CELL TECHNOLOGY
   - Reconfigurable Logic
   - Reprogrammable Cells
   - 100% Tested/100% Yields
   - High Speed Electrical Erasure (<100ms)
   - 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
   - Maximum Flexibility for Complex Logic Designs
   - Programmable Output Polarity
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
   - 100% Functional Testability
• APPLICATIONS INCLUDE:
   - Glue Logic for 3.3V Systems
   - DMA Control
   - State Machine Control
   - High Speed Graphics Processing
   - Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL16LV8 Connection Diagram

GAL16LV8  Connection Diagram

GAL16LV8 datasheet

GAL16LV8
PDF/DataSheet Download

Find GAL16LV8 Suppliers

  • ·GAL16LV8C-10LJ
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  • ·GAL16LV8C-15LJ
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  • ·GAL16LV8C-7LJ
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  • ·GAL16LV8D-3LJ
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  • ·GAL16LV8D-5LJ
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  • ·GAL16LV8ZD
  • LATTICE [Lattice Semiconductor] 
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  • ·GAL16V8
  • STMICROELECTRONICS [STMicroelectronics] 
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  • ·GAL16V8-10LNC 
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  • Electrically-Erasable PLD  
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