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Part Number: GF8 CMOS VCXO

 

 

 

 

Description: The GF8 VCXOs, are designed to be packaged in an industry-standard, 8 p...


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GF8 CMOS VCXO General Description


      The GF8 VCXOs, are designed to be packaged in an industry-standard, 8 pin Dual in Line package.The GF8 VCXOs would provide excellent phase jitter performance of which it would be less than 1ps.
      It has five features.The first one is about its frequency range which would be from 50.01MHz to 200MHz (15pF load).The second one is about its frequency range which would be from 50.01MHz to 320MHz (10pF load).The third one is that it has a LVCMOS output.The fourth one is about its supply voltage which would be 3.3 VDC.The last one is about its ultra low jitter which would be less than 1ps.
      Some important specifications have been concluded into several points.The first one is about its frequency range which would be from 50.01MHz to 200.0MHz with load 15pF and from 50.01MHz to 320.0MHz with load 10pF.The second one is about its supply voltage which would be 3.3 VDC ±5%.The third one is about its output logic which would be LVCMOS.The fourth one is about its integrated phase jitter which would be 0.4ps typical and 0.5ps maximum(for 155.250MHz).The fifth one is about its period jitter RMS which would be 3.0ps typical (for 155.250MHz).The sixth one is about its period jitter peak to peak which would be 20ps typical (for 155.250MHz).The seventh one is about its output load whicb would be 15pF.The eighth one is about its storage temperature which would be from -50° to +100°C.The ninth one is about its current consumption which would be 30mA maximum (15pF load) when less than 100MHz and 40mA maximum (15pF load) when larger than 100MHz.The tenth one is about its pulling range which would be from ±30ppm to ±150ppm.The eleventh one is about its Slope Polarity(Transfer function) which would be Monotonic and Positive. (An increase of control voltage always increases output frequency.).The last one is about its duty cycle which would be 50% ±5% measured at 50% Vdd.



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