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MFG:3636
Part Number: GM72V66841ET
MFG: 3636
Description: The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cell...
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GM72V66841ET
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DataSheet
General Description
GM72V66841ET General Description
The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally provided Clock.
The GM72V66841ET/ELT provides four banks of 2,097,152 word by 8 bit to realize high bandwidth with the Clock frequency up to 143 Mhz.
GM72V66841ET Maximum Ratings
| Parameter | Symbol | Value | Unit | Note |
| Voltage on any pin relative to VSS | VT | -0.5 to Vcc+0.5 (<= 4.6 (max)) |
V | 1 |
| Supply voltage relative to VSS | VCC | -0.5 to +4.6 | V | 1 |
| Short circuit output current | IOUT | 50 | mA | |
| Power dissipation | PT | 1.0 | W | |
| Operating temperature | Topr | 0 to +70 | C | |
| Storage temperature | Tstg | -55 to +125 | C |
GM72V66841ET Features
PC133/PC100/PC66 Compatible
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
3.3V single Power supply
LVTTL interface
Max Clock frequency
143/133/125/100MHz
4,096 refresh cycle per 64 ms
Two kinds of refresh operation
Auto refresh / Self refresh
Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
Programmable CAS latency : 2/3
4 Banks can operate independently or
simultaneously
Burst read/burst write or burst read/single
write operation capability
Input and output masking by DQM input
One Clock of back to back read or write
command interval
Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
JEDEC Standard 54Pin 400mil TSOP II
Package
-7(143MHz)/-75(133MHz)/-8(125MHz)
-7K(PC100,2-2-2)/-7J(PC100,3-2-2)
3.3V single Power supply
LVTTL interface
Max Clock frequency
143/133/125/100MHz
4,096 refresh cycle per 64 ms
Two kinds of refresh operation
Auto refresh / Self refresh
Programmable burst access capability ;
- Sequence:Sequential / Interleave
- Length :1/2/4/8/FP
Programmable CAS latency : 2/3
4 Banks can operate independently or
simultaneously
Burst read/burst write or burst read/single
write operation capability
Input and output masking by DQM input
One Clock of back to back read or write
command interval
Synchronous Power down and Clock
suspend capability with one Clock latency
for both entry and exit
JEDEC Standard 54Pin 400mil TSOP II
Package
GM72V66841ET Connection Diagram
GM72V66841ET
PDF/DataSheet Download
- Datasheet: GM72V66841ET
- File Size: 32768 KB
- Manufacturer: HYNIX [Hynix Semiconductor]
- Click here to Download
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