GN4121

Description


The GN4121 is is a Single Lane PCI Express-to-Local Bus Endpoint Bridge that is designed to work as a companion for FPGA devices to provide a complete bridging solution for general applications. In addition to a PCI Express compliant PHY interface, the GN4121 also contains the link and transaction layers, and an applications interface that is ideally suited to FPGA interfacing using a small number of pins.

Since the PCI Express transaction/link IP is hard-wired into the GN4121, there is no need to license PCIe IP. The level of integration and very low power operation of the GN4121 makes it an ideal alternative to using a PIPE PHY, where IP licensing and the cost of FPGA resources and power consumption is unattractive by comparison. Using the GN4121 allows FPGA resources to be spent on what differentiates the product rather than on implementing the PCI Express protocol.