GS8322Z72(C)

Features: • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• 2.5 V or 3.3 V +10%/10% core power supply• 2.5 V or 3.3 V I/O supply̶...

product image

GS8322Z72(C) Picture
SeekIC No. : 004356009 Detail

GS8322Z72(C): Features: • NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT...

floor Price/Ceiling Price

Part Number:
GS8322Z72(C)
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/3/28

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• NBT (No Bus Turn Around) functionality allows zero wait Read-Write-Read bus utilization; fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs
• 2.5 V or 3.3 V +10%/10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-Bump BGA package




Specifications

Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
0.5 to 4.6
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ +0.5 ( 4.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDD +0.5 ( 4.6 V max.)
V
IIN
Input Current on Any Pin
+/20
mA
IOUT
Output Current on Any I/O Pin
+/20
mA
PD
Package Power Dissipation
1.5
W
TSTG
Storage Temperature
55 to 125
TBIAS
Temperature Under Bias
55 to 125

Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.




Description

The GS8322Z18/36/72 is a 36Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the GS8322Z18/36/72 is switched from read to write cycles.

Because GS8322Z18/36/72 is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs of GS8322Z18/36/72 include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time.

Write cycles are internally self-timed and initiated by the rising edge of the clock input. GS8322Z18/36/72 feature eliminates complex offchip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.

The GS8322Z18/36/72 may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edgetriggered registers that capture input signals, the GS8322Z18/36/72 incorporates a rising edge triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge-triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.

The GS8322Z18/36/72 is implemented with GSI's high performance CMOS technology and is available in a JEDECstandard 119-bump, 165-bump or 209-bump BGA package.




Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
Boxes, Enclosures, Racks
LED Products
Cables, Wires - Management
Isolators
View more