Purchase GS8342R08, In-stock GS8342R08 From SeekIC.
Part Number: GS8342R08
Description: The GS8342R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Comm...
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GS8342R08
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DataSheet
General Description
GS8342R08 General Description
The GS8342R08/09/18/36E are built in compliance with the SigmaCIO DDR-II SRAM pinout standard for Common I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GS8342R08/09/18/36E SigmaCIO SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.
GS8342R08 Maximum Ratings
| Symbol | Description | Value | Unit |
| VDD VDDQ VREF VI/O VIN IIN IOUT TJ TSTG |
Voltage on VDD Pins Voltage in VDDQ Pins Voltage in VREF Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature |
0.5 to 2.9 0.5 to VDD 0.5 to VDDQ 0.5 to VDDQ +0.5 ( 2.9 V max.) 0.5 to VDDQ +0.5 ( 2.9 V max.) +/100 +/100 125 55 to 125 |
V V V V V mA dc mA dc °C °C |
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.
GS8342R08 Features
• Simultaneous Read and Write SigmaCIO™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 4 Read and Write
• 1.8 V +100/100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb devices
GS8342R08E-167
PDF/DataSheet Download
- Datasheet: GS8342R08E-167
- File Size: 1649573 KB
- Manufacturer: GSI [GSI Technology]
- Click here to Download
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GS8342R08 Relative Products
GS8342Q36A
GS8342Q18A
GS8342Q09A
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GS8342Q08
The GSQ8342Q08/09/18/36E are built in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 37,748,736-bit (36Mb) SRAMs. The GSQ8342Q08/09/18/36E SigmaQuad SRAMs are just one element in a family of low power, low ...
GS8342D36A
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