Features: • FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
ApplicationThe GS864418/36/72 is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
Specifications
| Symbol |
Description |
Value |
Unit |
| VDD |
Voltage on VDD Pins |
0.5 to 4.6 |
V |
| VDDQ |
Voltage in VDDQ Pins |
0.5 to 4.6 |
V |
| V I/O |
Voltage on I/O Pins |
0.5 to VDDQ +0.5 ( 4.6 V max.) |
V |
| VIN |
Voltage on Other Input Pins |
0.5 to VDD +0.5 ( 4.6 V max.) |
V |
| IIN |
Input Current on Any Pin |
+/20 |
mA |
| IOUT |
Output Current on Any I/O Pin |
+/20 |
mA |
| PD |
Package Power Dissipation |
1.5 |
W |
| TSTG |
Storage Temperature |
55 to 125 |
oC |
| TBIAS |
Temperature Under Bias |
55 to 125 |
oC |
DescriptionThe GS864418/36/72 is a 75,497,472-bit high performance ynchronous SRAM with a 2-bit burst address counter. Although of a ype originally developed for Level 2 Cache applications supporting igh performance CPUs, the GS864418/36/72 now finds application in ynchronous SRAM applications, ranging from DSP main store to etworking chip set support.
Addresses, data I/Os, chip enable (E1), address burst control inputs ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are ynchronous and are controlled by a positive-edge-triggered clock nput (CK). Output enable (G) and power down control (ZZ) of GS864418/36/72 are synchronous inputs. Burst cycles can be initiated with either ADSP r ADSC inputs. In Burst mode, subsequent burst addresses are enerated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function of GS864418/36/72 need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.
The function of the Data Output register GS864418/36/72 can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.
The GS864418/36/72 is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM GS864418/36/72 for either mode of operation using the SCD mode input
Byte write operation of GS864418/36/72 is performed by using Byte Write enable (BW) input combined with one or more individual byte writesignal (Bx). Inaddition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
The GS864418/36/72 operates on a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 3.3 V and 2.5 V compatible.
GS864472C Data Sheet
