Position: Home  > All Categories> Integrated Circuits (ICs) > GS880V37AT-225

GS880V37AT-225

Features: • Single Cycle Deselect (SCD) operation• 1.8 V +10%/10% core power supply• 1.8 V I/O supply•LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins• Default to Interleaved Pipeline mode• Byte W...

product image

GS880V37AT-225 Picture
See larger image
SeekIC No. : 004356180 Detail

GS880V37AT-225: Features: • Single Cycle Deselect (SCD) operation• 1.8 V +10%/10% core power supply• 1.8 V I/O supply•LBO pin for Linear or Interleaved Burst mode• Internal input resis...

GS880V37AT-225 Data Sheet

floor Price/Ceiling Price

Get Latest Price
Part Number:
GS880V37AT-225
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

SeekIC Buyer Protection PLUS - newly updated for 2013!

  • Escrow Protection.
  • Guaranteed refunds.
  • Secure payments.
  • Learn more >>

Month Sales

268 Transactions

Rating

evaluate  (4.8 stars)

Upload time: 2024/4/28

add to my favourite

Payment Methods

All payment methods are secure and covered by SeekIC Buyer Protection PLUS.

Notice: When you place an order, your payment is made to SeekIC and not to your seller. SeekIC only pays the seller after confirming you have received your order. We will also never share your payment details with your seller.
Product Details

Description



Features:

• Single Cycle Deselect (SCD) operation
• 1.8 V +10%/10% core power supply
• 1.8 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 100-lead TQFP package


Application

The GS880V37AT is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.




Pinout

Connection Diagram


Specifications

Symbol Description
Value
Unit
VDD Voltage on VDD Pins
0.5 to 3.6
V
VDDQ Voltage in VDDQ Pins
0.5 to 3.6
V
VCK Voltage on Clock Input Pin
0.5 to 3.6
V
VI/O Voltage on I/O Pins
0.5 to VDDQ +0.5 ( 3.6 V max.)
V
VIN Voltage on Other Input Pins
0.5 to VDD +0.5 ( 3.6 V max.)
V
IIN Input Current on Any Pin
+/20
mA
IOUT Output Current on Any I/O Pin
+/20
mA
PD Package Power Dissipation
1.5
W
TSTG Storage Temperature
55 to 125
TBIAS Temperature Under Bias
55 to 125
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.


Customers Who Bought This Item Also Bought

Margin,quality,low-cost products with low minimum orders. Secure your online payments with SeekIC Buyer Protection.
You may also be interested in :
Soldering, Desoldering, Rework Products
TGK-900M-B
TGK-900M-1.6D
RF and RFID
X3C26P1-30S
1P620S
Circuit Protection
A50QS75-4Y
F-17*77
Fans, Thermal Management
3610ML-05W-B49
1608KL-05W-B39
Tapes, Adhesives
803
AC452-2
Semiconductor Modules
2DI300A-050-03
7MBR25SA-120-50
View more