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HD49335NP/HNP

Features: ·Suppresses low-frequency noise, which output from CCD by the correlated double sampling. ·The S/H response frequency characteristics for the reference level can be adjusted usingvalues of external parts and registers.·High sensitivity is achieved due to the high S/N ratio and a wide dyn...

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HD49335NP/HNP: Features: ·Suppresses low-frequency noise, which output from CCD by the correlated double sampling. ·The S/H response frequency characteristics for the reference level can be adjusted usingvalues of...

HD49335NP/HNP Data Sheet

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HD49335NP/HNP
Supply Ability:
5000

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Product Details

Description



Features:

·Suppresses low-frequency noise, which output from CCD by the correlated double sampling. 
·The S/H response frequency characteristics for the reference level can be adjusted using 
   values of external parts and registers. 
·High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided
   by a PG amplifier.  PGA, pulse timing, standby mode, etc., is achieved via a serial interface. 
·High precision is provided by a 10-bit-resolution A/D converter. 
·Difference encoded gray code can be selected as an A/D output code. 
·It is effective in suppression of solarization 
   (wave pattern).  It is patented by Renesas. 
·Timing generator generates the all of pulse which are needed for CCD driving. 
 


Pinout

Connection Diagram


Specifications

Item Symbol Ratings Unit
Power supply voltage VDD 4.1 V
Analog input voltage VIN -0.3 to ADD +0.3
V
Digital input voltage VI -0.3 to DVDD +0.3
V
Operating temperature range Ta -10 to +75
Power dissipation Pt 750 mW
Storage temperature Tstg -55 to +125
Storage temperature Vopr 2.70 to 3.30 V

Note: AVDD  , AV SS are analog power source systems of CDS, PGA, and ADC. 
         DVDD  1, DVSS 1 are digital power source systems of CDS, PGA and ADC. 
         DVDD2, DV SS 2 are buffer power source systems of ADC output. 
         DVDD3, DV SS 3 are general digital power source systems of TG. 
         DVDD4, DV SS 4 are buffer power source systems of H1 and H2. 
              `Pin 2 multi bonds the DVSS 1 and DVSS 2 
              `When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output
                 When Hi, pin 41 = Vgate input, pin 39 = ADCK input 
 


Description

The HD49335NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in ip.

There are address map and timing generator charts besides this specification of HD49335NP/HNP.  May be contacted to our s department if examining the details.




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