HD74AC195

Features:

·  Shift Right and Parallel Load Capability
·  J-K (D-Type) Inputs to First Stage
·  Complement Output from Last Stage
·  Asynchronous Master Reset
·  Outputs Source/Sink 24 mA


Pinout




Specifications

Item	Symbol	Max	Unit	Condition
Maximum quiescent supply current	ICC	80	A	VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case
Maximum quiescent supply current	ICC	8.0	A	VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C

Description

This HD74AC195 shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q0 towards Q3.

Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode is entered at the J-K inputs. These inputs of HD74AC195 allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table.