HD74ALVCH16821

Features: * VCC = 2.3 V to 3.6 V* Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)* Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)* High output current 24 mA (@VCC = 3.0 V)* Bus hold on data inputs eliminates the need for external pullup / pulldown resistorsSpecificatio...

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SeekIC No. : 004360571 Detail

HD74ALVCH16821: Features: * VCC = 2.3 V to 3.6 V* Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)* Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)* High output current 24 mA (@VCC = 3.0 ...

floor Price/Ceiling Price

Part Number:
HD74ALVCH16821
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/25

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Product Details

Description



Features:

*  VCC = 2.3 V to 3.6 V
*  Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 C)
*  Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25 C)
*  High output current 24 mA (@VCC = 3.0 V)
*  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors



Specifications

Item

Symbol

Ratings

Unit

Test Conditions

Supply voltage range

VCC

0.5 to 4.6

V

 


Input voltage range *1

VI

0.5 to 4.6

V

 


Output voltage range *1, 2

VO

0.5 to VCC  +0.5

V

 

Input clamp current

IIK

50

mA

VI < 0

Output clamp current

IOK

50

mA

VO < 0 or VO > VCC

Continuous output current

IO

50

mA

VO = 0 to VCC

VCC, GND current / pin

ICC or IGND

100

mA

 

Maximum power dissipation

at Ta = 55 C (in still air) *3

PT

1

mW

 

Storage temperature

Tstg

65 to 150

C

 




Description

The HD74ALVCH16821 can be used as two 10-bit flip flops or one 20-bit flip flop.  The 20 flip flops are edge triggered D-type flip flops.  On the positive transition of the clock (CLK) input, the HD74ALVCH16821 provides true data at the Q outputs.  A buffered output enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low levels) or a high impedance state.  In the high impedance state, the outputs neither load nor drive the bus lines significantly.  The high impedance state and increased drive provide the capability to drive bus line without need for interface or pullup components.  The output enable (OE) input does not affect the internal operations of the flip flops.  Old data can be retained or new data can be entered while the outputs are in the high impedance state.  Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.




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