HD74ALVCH16831

Features:

*  V_CC = 2.3 V to 3.6 V
*  Typical V_OL ground bounce < 0.8 V (@V_CC = 3.3 V, Ta = 25°C)
*  Typical V_OH undershoot > 2.0 V (@V_CC = 3.3 V, Ta = 25°C)
*  High output current ±24 mA (@V_CC = 3.0 V)
*  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors


Pinout




Specifications

Item	Symbol	Ratings	Unit	Conditions
Supply voltage	VCC	0.5 to 4.6	V
Input voltage*1	VI	0.5 to 4.6	V
Output voltage *1, 2	VO	0.5 to VCC +0.5	V
Input clamp current	IIK	50	mA	VI < 0
Output clamp current	IOK	50	mA	VO < 0 or VO > VCC
Continuous output current	IO	50	mA	VO = 0 to VCC
VCC , GND current / pin	ICC or IGND	100	mA
Maximum power dissipation at Ta = 55 C (in still air)*3	PT	1	W	TVSOP
Storage temperature	Tstg	65 to 150	C

Description

This HD74ALVCH16831 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation.  The device is ideal for use in applications in which a single address bus is driving four separate memory locations.  The HD74ALVCH16831 can be used as a buffer or a register, depending on the logic level of the select (SEL)  input.  When SEL is logic high, the device is in the buffer mode.  The outputs follow the inputs and are controlled by the two output enable (OE) controls.  Each OE controls two groups of nine outputs.  When SEL is logic low, the device is in the register mode.  The register is an edge triggered D-type flip flop.  On the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers. OE controls operate the same as in buffer mode.  When OE is logic low, the outputs are in a normal logic state (high or low logic level).  When OE is logic high, the outputs are in the high impedance state.  To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver.  SEL and OE do not affect the internal operation of the flip flops.  Old data can be retained or new
data can be entered while the outputs are in the high impedance state.  Active HD74ALVCH16831 bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.