Features: · Supports unregulated battery operation down to 2.7 V· Bus hold on data inputs eliminates the need for external pullup resistors.· Distrlbuted VCC and GND pin conflguration minimizes high speed switching noisePinoutSpecifications Item Symbol Ratings Unit Conditions ...
HD74ALVCH16835: Features: · Supports unregulated battery operation down to 2.7 V· Bus hold on data inputs eliminates the need for external pullup resistors.· Distrlbuted VCC and GND pin conflguration minimizes high...
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Item |
Symbol |
Ratings |
Unit |
Conditions |
Supply voltage |
VCC |
0.5 to 4.6 |
V |
|
Input voltage *1 |
VI |
0.5 to 4.6 |
V |
|
Output voltage *1, 2 |
VO |
0.5 to VCC +0.5 |
V |
|
Input clamp current |
IIK |
-50 |
mA |
VI<0 |
Output clamp current |
IOK |
±50 |
mA |
VO<0 or VO >VCC |
Continuous output current |
IO |
±50 |
mA |
VO = 0 to VCC |
VCC, GND current / pin |
ICC or IGND |
±100 |
mA |
|
Maximum power dissipation at Ta = 55°C (in still air)*3 |
PT |
1 |
W |
TSSOP |
Storage temperature |
Tstg |
65 to 150 |
°C |
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating condition" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
Notes: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The maximum power dissipation is calculated using a junction temperature of 150°C and board trace length of 750 mils
The HD74ALVCH16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is low, the A bus data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, the output ebable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active HD74ALVCH16835 bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.