HD74ALVCH16836

Features:

*  VCC = 2.3 V to 3.6 V
*  Typical V_OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
*  Typical V_OH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
*  High output current ±24 mA (@VCC = 3.0 V)
*  Bus hold on data inputs eliminates the need for external pullup / pulldown resistors


Pinout




Specifications

Item	Symbol	Ratings	Unit	Conditions
Supply voltage	VCC	0.5 to 4.6	V
Input voltage*1	VI	0.5 to 4.6	V
Output voltage *1, 2	VO	0.5 to VCC +0.5	V
Input clamp current	IIK	50	mA	VI < 0
Output clamp current	IOK	50	mA	VO < 0 or VO > VCC
Continuous output current	IO	50	mA	VO = 0 to VCC
VCC , GND current / pin	ICC or IGND	100	mA
Maximum power dissipation at Ta = 55 C (in still air)*3	PT	1	W	TSSOP
Storage temperature	Tstg	65 to 150	C

Description

This HD74ALVCH16836 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation.Data flow from A to Y is controlled by the output enable (OE) input.  The HD74ALVCH16836 operates in the transparent mode when the latch enable (LE) input is low.  The A data is latched if the clock (CLK) input is held at a high or low logic level.  If LE is high, the A data is stored in the latch flip flop on the low to high transition of CLK.  When OE is high, the outputs are in the high impedance state.

To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active HD74ALVCH16836 bus hold circuitry is provided to hold unused or floating inputs at a valid logic level.