HD74BC574A

Features: ` Input/Output are at high impedance state when power supply is off.` Built in input pull up circuit can make input pins be open, when not used.` TTL level input` Wide operating temperature range Ta = 40 to + 85°CPinoutSpecifications Item Symbol Rating Unit Supply volt...

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HD74BC574A Picture
SeekIC No. : 004360592 Detail

HD74BC574A: Features: ` Input/Output are at high impedance state when power supply is off.` Built in input pull up circuit can make input pins be open, when not used.` TTL level input` Wide operating temperatur...

floor Price/Ceiling Price

Part Number:
HD74BC574A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/17

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Product Details

Description



Features:

`  Input/Output are at high impedance state when power supply is off.
`  Built in input pull up circuit can make input pins be open, when not used.
`  TTL level input
`  Wide operating temperature range Ta = 40 to + 85°C



Pinout

  Connection Diagram


Specifications

Item
Symbol
Rating
Unit
Supply voltage
VCC
0.5 to +7.0
V
Input diode current
IIK
±30
mA
Input voltage
VIN
0.5 to +7.5
V
Output voltage
VOUT
0.5 to +7.5
V
Off state output voltage
VOUT(off)
0.5 to +5.5
V
Storage temperature
Tstg
65 to +150
°C
Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.


Description

The HD74BC574A provides high drivability and operation equal to or better than high speed bipolar standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5 of high speed bipolar logic IC, when the frequency is 10 MHz. The HD74BC574A has eight edge triger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the strage elements.




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