Features: ` Supports PC133 and meets "PC SDRAM registered DIMM specification, Rev. 1.1"
` Phase-lock loop clock distribution for synchronous DRAM applications
` External feedback (FBIN) pin is used to synchronize the outputs to the clock input
` No external RC network required
` Support spread spectrum clock (SSC) synthesizers
` Supports frequencies up to 140 MHz
` 0 to 85°C operating rangePinout
Specifications
|
Item |
Symbol |
Ratings |
Unit |
Conditions |
| Supply voltage |
VCC |
0.5 to 4.6 |
V |
|
| Input voltage *1 |
VI |
0.5 to 4.6 |
V |
|
| Output voltage *1,2 |
VO |
0.5 to VCC +0.5 |
V |
|
| Input clamp current |
IIK |
-50 |
mA |
VI < 0 |
| Output clamp current |
IOK |
±50 |
mA |
VO<0 or VO>VCC |
| Continuous output current |
IO |
±50 |
mA |
VO = 0 to VCC |
| Supply current |
ICC or IGND |
±100 |
mA |
|
| Maximum power dissipation at Ta = 55°C (in still air)*3 |
PT |
0.7 |
W |
|
| Storage temperature |
Tstg |
65 to 150 |
°C |
|
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
DescriptionThe HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. HD74CDCF2509B uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The HD74CDCF2509B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks.The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
HD74CDCF2509B Data Sheet
