HD74HC137

Features: · High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)· High Output Current: Fanout of 10 LSTTL Loads· Wide Operating Voltage: VCC = 2 V to 6 V· Low Input Current: 1 µA max· Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)PinoutDescriptionThe H...

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HD74HC137 Picture
SeekIC No. : 004360626 Detail

HD74HC137: Features: · High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)· High Output Current: Fanout of 10 LSTTL Loads· Wide Operating Voltage: VCC = 2 V to 6 V· Low Input Current: 1 µ...

floor Price/Ceiling Price

Part Number:
HD74HC137
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Features:

·  High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
·  High Output Current: Fanout of 10 LSTTL Loads
·  Wide Operating Voltage: VCC = 2 V to 6 V
·  Low Input Current: 1 µA max
·  Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)



Pinout

  Connection Diagram


Description

The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs.

All of the outputs are high unless G1 is high and G2 is low. The HD74HC137 is ideally suited for the implementation of glitchfree decoders in stored-address applications in bus oriented systems.


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