HD74HCT563

`  LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
`  High Speed Operation: t_pd (D to Q, Q) = 13 ns typ (C_L = 50 pF)
`  High Output Current: Fanout of 15 LSTTL Loads
`  Wide Operating Voltage: V_CC = 4.5 to 5.5 V
`  Low Input Current: 1 A max
`  Low Quiescent Supply Current: I_CC (static) = 4 A max (Ta = 25°C)

When the latch enable (LE) input is high, the Q outputs of HD74HCT563 will follow the inversion of the D inputs and the Q outputs of HD74HCT573 will follow the D inputs.

When the HD74HCT563 latch enable goes low, data at the D inputs will be retained at the outputs until latch enabled returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.